Openings for Technical Architects @ Infineon

Publish Date: 13th September 2013
Company Name: Charter Global

Location: Bangalore
Experience: 8 – 10 years
Contact Mail : Please send resumes to
Company URL:
Job Description :  
  • Working with the team of SOC design methodology, flow and implementation engineers. 
  • Work on Synthesis, STA, DFT, Spyglass and timing constraints development for complex designs.
  • Develop fullchip/interfaces timing constraints with several IPs for functional and test modes interacting with RTL designers and understanding design specification.
  • Responsible for full chip timing closure for all modes and timing characterization of IO interfaces.
  • Work closely with Timing methodology/signoff team and design teams to improve the flow which helps faster timing closure.
  • Responsible for debugging current tool and flow issues working closely with EDA vendors and drive them for new features. 
  • Adapting Infineon flow and tools for faster and reliable tape out of complex designs. Work as integral part of the team in Global environment.


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